This invention relates generally to a programmable logic circuit and, more particularly, to improvements in a programmable logic circuit commonly referred to as a programmable array logic, or PAL (note: PAL is a trademark of Monolithic Memories, Inc.).
U.S. Pat. No. 4,124,899 to Birkner, et al. shows a programmable logic circuit which includes a programmable array or matrix interconnecting circuit inputs and the inputs to a plurality of AND gates. The outputs of the AND gates, which logically are products of selected polarities of selected inputs, are subgrouped and are nonprogrammably connected as inputs to individual, specified OR gates. The outputs of the OR gates are, logically speaking, sums of these product terms.
Making the OR gate inputs nonprogrammable sacrifices a degree of design flexibility when comparing these devices to programmable logic arrays (PLA's) which are programmable in both AND and OR arrays. However, the reduction in IC chip size and improvement in speed for the PAL circuit is substantial and results in advantages which more than offset the reduction in flexibility.
One problem in the design of PAL circuits stems from the fact that PAL's have a fixed number of product terms (PT's) per output. The number of PT's to be allocated to each output has been a recurring question for PAL designers. Too few product terms per output unduly limits flexibility and utility of the device. However, each additional product term increases the size of the IC, reduces overall device speed, and increases power consumption. In an attempt to address this problem, some devices offer a different number of PT's on each output. While this approach may be satisfactory in certain situations, problems are still likely to arise in applications requiring some degree of design flexibility.
An object of the present invention is to provide a PAL circuit architecture which allows two or more of the sum of the product outputs to share all or some portion of the product terms.
Another object of the present invention is to provide a PAL circuit architecture which allows the circuit designer to programmably allocate individual product terms to one or more of the circuit outputs.
Yet another object of the present invention is to provide for electrical isolation of the device outputs to allow one product term to be simultaneously shared by more than one of the device outputs.
These objects are attained in a programmable logic circuit comprising: an array having a plurality of inputs and a plurality of outputs and circuitry for combining selected ones of the inputs at each of the outputs; circuitry for connecting a first set of the array outputs to a first of a plurality of logic circuit outputs; circuitry for connecting a second set of the array outputs to a second logic circuit output; wherein the first set of array outputs includes less than all of the available outputs; and wherein this first set includes at least one output in common with the second set of array outputs. In a preferred embodiment of the invention, the second set of array outputs includes less than all of the available array outputs.
Restated in slightly different terms, the programmable logic circuit of the present invention comprises: an array having a plurality of inputs for receiving input terms and a plurality of outputs and circuitry for combining selected ones of the input terms at each of the array outputs; circuitry for connecting a first array output to a first of a plurality of outputs of the logic circuit; circuitry for connecting a second array output to a second logic circuit output; and circuitry for selectively connecting a third array output to either or both of the first and second logic circuit outputs. The array in the programmable logic circuit is preferrably a product term generator, such as an AND array, and the combinations of input terms at the array outputs are product terms (PT's).
The circuitry for connecting each of the array outputs to the logic circuit outputs comprises a programmable element serially connected to isolating circuitry for electrically isolating the first and second logic circuit outputs. The isolating circuitry preferably includes a three-terminal device having a first terminal connected to the programmable element, a second terminal connected to a power source and a third terminal connected to one of the array outputs. In a preferred embodiment, the three-terminal device is a transistor having a control terminal (i.e., the base terminal) connected to the array output.
The PAL architecture of the present invention increases the effective number of PT's without increasing the actual total number. The shared product terms allow two outputs having equations which contain the same PT to be connected to one physical PT, rather than requiring that PT to be generated twice as is common in a conventional PAL circuit. Thus, the new architecture increases the effective number of PT's without increasing power consumption or degrading device speed.
It should be noted that the programmable logic circuit of the present invention is intended to include devices which are mask-programmable, as well as those that are field programmable. With the latter type, the programming feature of the present invention allows the user to recover from programming errors and make design changes without necessarily having to sacrifice a device. However, for particular high volume applications, a mask-progammable array which embodies the shared product terms of the present invention may be cost effective.
Other objects, advantages and novel features of the present invention will become apparent from the following detailed description of the invention when considered in conjunction with the accompanying drawings.